Method and device to form high quality oxide layers of different thickness in one processing step

ABSTRACT

The present invention relates to a method for forming high quality oxide layers of different thickness over a first and a second semiconductor region in one processing step. The method comprises the steps of: doping the first and the second semiconductor region with a different dopant concentration, and oxidising, during the same processing step, both the first and the second semiconductor region under a temperature between 500° C. and 700° C., preferably between 500° C. and 650° C. A corresponding device is also provided. Using a low-temperature oxidation in combination with high doping levels results in an unexpected oxidation rate increase.

The present invention relates to a method and device for forming highquality oxide layers of different thickness during one and the sameprocessing step. This can be used for example for isolating a memorygate stack from an access gate in a non-volatile memory (NVM) cell suchas a 2 transistor (2-T) flash memory cell.

Flash memories or flash memory cells comprise a MOSFET with a floatinggate between a control gate and a channel region. With the improvementof fabrication technologies, the floating gate size has been reduced tonanometer scale. These devices are basically miniature EEPROM cells inwhich electrons (or holes) are injected in a nano floating gate bytunnel effect through an oxide barrier. Charges stored in the floatinggate modify the device threshold voltage. A schematic representation ofa 2 transistor (2-T) flash EEPROM cell 10 is depicted in FIG. 1. Itcomprises a storage transistor or memory gate stack 12, and a selectingtransistor or access gate 14. A schematic cross-section through acompact 2-T flash EEPROM cell 10 is given in FIG. 2.

In such memory cells 10, the access gate 14 and the memory gate stack 12are isolated from each other by an isolation spacer 16. In a typical 2-Tflash memory cell, this isolation is a TEOS (TetraethylOrthosilicate—Si(OC₂H₅)₄) spacer.

TEOS is a liquid source oxide deposition with excellent uniformity, stepcoverage and film properties. Disadvantages in using TEOS include itshigh temperature and liquid source requirements. After applying the TEOSspacers, a plasma etch thereof is carried out. Generally, the TEOSspacers are over-etched, which means that the silicon substrate 18 atthe location where the gate oxide 20 of the access gate 14 has to begrown, is damaged. This results in a degradation of the siliconinterface where high quality gate oxide 20 has to be formed for theaccess gate or selecting transistor 14.

It is known from X. Tang et al., “Self-aligned silicon-on-insulator nanoflash memory device”, Solid State Electronics 44 (2000), p.2259-2²⁶⁴that the silicon oxidation rate depends on the concentration of dopingimpurities such as e.g. arsenic (As). For short times, the relationshipbetween the oxide thickness (X₀) and oxidation time (t) is given by:$\frac{X_{o}}{t} = A$where A is a linear oxidation rate constant determined by the intrinsiclinear oxidation rate constant, and depending on the partial pressure,on free carrier concentration, on chlorine concentration and on dopinglevel of the silicon. Increasing doping levels enhances the siliconoxidation rate, which means that, for oxidations carried out under asame temperature, silicon with a higher doping level of a certain dopantleads to a thicker oxide layer thereupon than silicon with a lowerdoping level of the same dopant.

U.S. Pat. No. 6,015,736 describes a system and method for providing aflash memory cell on a semiconductor. On the semiconductor substrate, atunnel oxide is grown, on top of which a gate stack comprising afloating gate, an inter-layer and a control gate is provided usingconventional methods. The gate stack is then oxidized at a differentialrate from oxidation of the surface of the underlying semiconductor. Thedifferential rate of oxidation allows the gate stack to oxidize muchmore quickly than a portion of the semiconductor that is adjacent to thegate stack. This is obtained, in a preferred embodiment, by providing animplant at a high angle to impact the side of the gate stack. Theimplant allows the gate stack, which otherwise would oxidize atapproximately the same rate as the semiconductor, to oxidize at a higherrate. According to another embodiment, the surface of the side of apolysilicon gate is treated so as to be amorphous, because an oxide maygrow more rapidly on an amorphous surface than on a crystalline surface.

The prior art methods described above result in a gate stack isolationlayer that is about a factor 3 thicker than the oxidation layer providedon the undoped silicon substrate.

It is an object of the present invention to overcome the disadvantagesof the prior art. More particularly, it is an object of the presentinvention to obtain high quality oxide layers of different thickness inone processing step.

It is a further object of the present invention to obtain, in oneprocess step, high quality oxide layers of at least a first and a secondthickness, the first thickness being at least a factor 10 higher thanthe second thickness.

Yet a further object of the present invention is to provide a method forisolating a memory gate stack from an access gate in a non-volatilememory cell. It is also an object of the present invention to provide anon-volatile memory cell of which the memory gate stack is isolated fromthe access gate.

The above objectives are accomplished by the methods and devicesaccording to the present invention.

A method according to the present invention for forming high qualityoxide layers of different thickness over a first and a secondsemiconductor region in one processing step comprises the steps of:

-   -   doping the first and the second semiconductor regions with a        different dopant concentration, and    -   oxidising both the first and the second semiconductor region        during the same processing step at a temperature between 500° C.        and 700° C., preferably between 500° C. and 650° C.

According to an embodiment of the present invention, the dopantconcentration of the first semiconductor region is at least a factor 10higher than the dopant concentration of the second semiconductor region.

The doping step may be carried out with n-type dopants or with p-typedopants.

The method may furthermore comprise, before the doping step, a step ofproviding a first and a second semiconductor region. This step ofproviding the first semiconductor region may comprise providing a dopedgate stack. The step of providing a doped gate stack may comprise thesteps of:

-   -   growing a tunnel oxide on the semiconductor,    -   depositing floating gate polysilicon on the tunnel oxide,    -   doping the floating gate polysilicon, thus forming doped        floating gate polysilicon,    -   depositing an interlayer dielectric on the doped floating gate        polysilicon,    -   depositing control gate polysilicon on the interlayer        dielectric, and    -   doping the control gate polysilicon.

A method according to the present invention wherein a doped gate stackis provided, may further comprise a step of patterning the doped gatestack.

According to an embodiment of the present invention, the oxidising stepis a wet oxidation process.

The present invention also provides a non-volatile memory element havinga memory gate stack isolated from an access gate obtained by any of themethods according to the present invention. The element may be a 2-Tflash EEPROM cell.

These and other features and advantages of the present invention willbecome apparent from the following detailed description, taken inconjunction with the accompanying drawings, which illustrate, by way ofexample, the principles of the invention. This description is given forthe sake of example only, without limiting the scope of the invention.The reference figures quoted below refer to the attached drawings.

FIG. 1 is a schematic representation of a 2-T flash EEPROM cell.

FIG. 2 is a schematic vertical cross-section through a compact 2-T flashEEPROM cell.

FIGS. 3A to 3D show different steps in the fabrication of a 2-T flashEEPROM cell.

FIG. 4 is a graph showing the oxidation rate dependence on the siliconsurface dopant concentration for different implants, at 700° C.

FIG. 5A shows the expected oxidation rate increase for As-doped Si infunction of dopant concentration, for a 10 nm thick oxide obtained bywet oxidation at 650° C. and 700° C.

FIG. 5B shows the oxidation rate increase for As-doped Si in function ofdopant concentration, for a 10 nm thick oxide obtained by wet oxidationat 700° C. Expected oxidation rate increase is compared toexperimentally obtained oxidation rate increase.

FIG. 5C shows the oxidation rate increase for As-doped Si in function ofdopant concentration, for a 2.8 nm thick oxide obtained by wet oxidationat 650° C. Expected oxidation rate increase is compared toexperimentally obtained oxidation rate increase. In the differentdrawings, the same reference figures refer to the same or analogouselements.

The present invention will be described with respect to particularembodiments and with reference to certain drawings but the invention isnot limited thereto but only by the claims. The drawings described areonly schematic and are non-limiting.

As an example, it will be explained how a 2-T flash EEPROM cell can bemanufactured according to the present invention.

According to an embodiment of the present invention, as shown in FIG.3A, first a conventional stacked gate forming the memory gate stack 12is formed. This may e.g. be done by growing, on a silicon substrate 18,a tunnel barrier, which is a thin tunnel oxide layer 22 of for example 7nm thick. On top of this tunnel oxide layer, a first polysilicon layer24 may be deposited. This layer 24 may for example be 200 nm thick.Thereafter, the first polysilicon layer 24 is highly doped, preferablywith n-type dopants 26, such as arsenic (As) or phosphorus (P), leadingto a doped first polysilicon layer 28. With highly doped is meant adopant concentration of at least 6e19/cm³, preferably 3e20/cm³ or more,still more preferred 1e21/cm³ or more. This doped first polysiliconlayer 28 will later form a floating gate. On top of the doped firstpolysilicon layer 28, an interlayer dielectric 30 may be deposited, asshown in FIG. 3B. Such an interlayer dielectric 30 is also called an ONOlayer. A, for example, 200 nm thick second polysilicon layer 32 may bedeposited on top of the interlayer dielectric 30, and again this layer32 is highly doped, preferably with n-type dopants 34, such as As or P,leading to a doped second polysilicon layer 36. With highly doped ismeant a dopant concentration of at least 6e19/cm³, preferably 3e20/cm³or more, still more preferred 1e21/cm³ or more. This doped secondpolysilicon layer 36 will later form a control gate. An optionalisolating layer (e.g. nitride or oxide) may be provided on top (notshown in the drawings).

It is to be appreciated that the thickness of the interlayer dielectric30 in the figures is shown to be relatively the same as the other layers28, 36 for ease of understanding; however, the ONO layer is actuallyvery thin relative to the first polysilicon layer 24/28 and the secondpolysilicon layer 32/36.

A resist is lithographically patterned over portions of doped secondpolysilicon layer 36. Then the doped second polysilicon layer 36 isetched away at portions not covered by the resist. Also the dielectricinterlayer 30 is substantially etched away using conventionaltechniques. The doped first polysilicon layer 28 is substantially etchedaway using conventional etching techniques, an the tunnel oxide layer 22is substantially etched away. That way, the stack is patterned, and astacked gate 38 is formed, as shown in FIG. 3C. Preferably, the deviceis cleaned, so as to leave bare the surface of the silicon substrate 18where no stacked gate 38 is present.

After formation of this stacked gate 38, its sidewalls have to beisolated and a gate oxide 20 (see FIG. 2) at the bottom next to it hasto be grown. According to the present invention, this is all done in onego, more specifically by a low-temperature oxidation step. With alow-temperature oxidation step is meant an oxidation carried out at atemperature of 700° C. or below, preferably between 500° C. and 700° C.,and more preferred between 500° C. and 650° C. The oxidation steppreferably is a wet oxidation, and the result is shown in FIG. 3D.

By having chosen a high doping level in both the first polysilicon layer28 and the second polysilicon layer 36, coupled to a low temperature wetoxidation, the thickness of the oxide 40 on the side walls of the highlydoped stacked gate 38 can be tuned in a range of gate thickness toalmost twenty times the thickness of the oxide grown on the undopedsilicon substrate 18. After this step, both the gate oxide for theaccess gate transistor 14 as well as the isolation 16 between the memorygate stack 12 and the access gate transistor 14 have been created.

The spacer oxide 16 is thus grown at the same time as the thermaloxidation of the gate oxide 20 of the access transistor 14. As it isknown from the prior art, the oxidation rate is dependent on the dopantconcentration. For example, the oxidation rate is increased for highlydoped As and P doped silicon. Since the oxidation speed depends on thedoping level, the oxide layer grows faster on the comparatively stronglydoped region of silicon (the stacked gate 38) than on the comparativelyweakly doped surrounding silicon zone (the silicon substrate 18) duringthe oxidation process.

But according to an aspect of the present invention, the oxidation rateis furthermore, unexpectedly, strongly enhanced by using a lowtemperature oxidation. Because the control gate 36 and floating gate 28are highly doped, a thick oxide 40 is grown there under low temperatureoxidation. This oxide has a much better quality than the conventionalTEOS spacer does. With low temperature oxidation is meant an oxidationcarried out at temperatures below 700° C., preferably between 500° C.and 700° C. At 700° C., the increase in oxidation rate is a factor 10,and at 650° C., the increase in oxidation rate may even amount to afactor 20.

For example if a P doping 26, 34 in the strongly doped regions 28, 36 ofthe above 2-T flash EEPROM cell 10 is approximately 3×10²⁰ at/cm², anadditional silicon oxide 40 with a thickness of approximately 30 nm willgrow at the sidewalls of the highly doped stacked gate 38 in the case ofthermal oxidation at 700° C. for 15 min in O₂, whereas no more than 3 nmsilicon oxide 42 is formed on the undoped silicon substrate 18.

For further manufacturing of the 2-T flash EEPROM cell, standardprocessing can be used, until a device as schematically shown incross-section in FIG. 2 is obtained.

An advantage of the present invention is that the gate oxide 20 of theaccess transistor 14 is improved, and that the spacer oxide 16 is muchthicker than the ones obtained in prior art methods, which results in abetter isolation.

The devices obtained may be used in embedded non-volatile memories.

It should be appreciated that although specific layering materials,layering thicknesses, dopant concentrations and process steps areidentified in the above preferred embodiment, any materials,thicknesses, dopant concentrations and processes suitable for carryingout the present invention may be employed and fall within the scope ofthe claims.

The present invention is described in terms of providing a single cellusing particular surface treatments. However, one of ordinary skill inthe art will readily recognize that this method and system will operateeffectively for other methods including other steps and which providee.g. multiple cells in a single process. Moreover, the method and systemwill function effectively for other treatments or systems having a largeenough differential oxidation rate between two differently dopedsemiconductor regions. The technique can be extended to other similarprocesses where there is need to form high quality oxide layers ofdifferent thickness in one processing step.

FIG. 4 shows the oxidation rate dependence on the dopant concentrationat the Silicon surface for P (Phosphorus), As (Arsenic), B (Boron) andBF₂ implants at 700° C. The graph is a summary of data for experimentsrun at different times and in different clean rooms: data indicated witha black square are obtained at the Philips NatLab FABWAG clean rooms,while data indicated with a white circle are obtained at the IMECP-LINE. The oxidation of the undoped Silicon was measured to be 10 nmfor oxidation at 700° C. It can be seen that, for an As implant, dopinglevels of 1.186e19 cm⁻³ do not increase the oxidation rate at 700° C.For As doping levels of 1.029e20 cm⁻³, there is a slight increase inoxidation rate at 700° C., but for doping levels of 9.089e20 cm⁻³ theoxidation rate is increased with a factor 8. For higher As dopinglevels, the oxidation rate is even increased with a higher factor.

The increase in oxidation rate with doping levels is especiallyimportant for n-type impurities (such as e.g. P and As).

FIG. 5A shows the expected oxidation rate increase for As-doped Si infunction of dopant concentration, for a 10 nm thick oxide obtained bywet oxidation at 650° C. and 700° C. In order to evaluate the expectedoxidation rate increase results, an industry-standard semiconductorprocess simulation tool from AVANT!, TSUPREM4, is used. Although onlyresults for As-doped Si are given in the present patent application, thesame conclusions can be drawn for P-doping. For As-doped Si oxides witha thickness of 10 nm, obtained by wet oxidation, it can be seen fromFIG. 5A that the oxidation rate is expected to increase with the dopinglevel. In this thickness range, oxidation is expected to decrease withdecrease in temperature.

However, according to the present invention, and as shown in FIG. 5B andFIG. 5C, the combination of a high doping level and a low oxidationtemperature results in a higher oxidation rate increase than expected.

FIG. 5B compares the expected oxidation rate increase, at an oxidationtemperature of 700° C., with experimentally obtained values. It can beseen that for doping levels of 1 e21 cm⁻³ or higher, the oxidation rateincrease is a factor 4 or more higher than expected.

For lower temperatures, for example 650° C. as shown in FIG. 5C, a stilllarger discrepancy between the experimentally obtained oxidation rateincrease and the expected values is obtained.

For temperatures below 700° C. and doping levels above 1e21 cm⁻³, anincrease of oxidation rate to values of 10 or more is obtained, whichmakes this method useful to make non-volatile memory elements by formingoxide layer of different thickness in one processing step. In suchmemory elements, it is typically desired to have a thin gate dielectricof a thickness of 3 nm or less, and a gate oxide between the accesstransistor and the control gate of a thickness of 30 nm or more. Ifthose oxides are to be made in one go, there must be an oxidation ratedifference of at least 10.

1. A method for forming high quality oxide layers of different thicknessover a first and a second semiconductor region in one processing step,comprising the steps of: doping the first and the second semiconductorregions with a different dopant concentration, and oxidising both thefirst and the second semiconductor region during the same processingstep at a temperature between 500° C. and 700° C., preferably between500° C. and 650° C.
 2. A method according to claim 1, wherein the dopantconcentration of the first semiconductor region is at least a factor 10higher than the dopant concentration of the second semiconductor region.3. A method according to claim 2, wherein the dopant concentration ofthe first semiconductor region is at least 1×10²¹ cm^(−3.)
 4. A methodaccording to claim 1, wherein the doping step is carried out with n-typedopants.
 5. A method according to claim 1, wherein the doping step iscarried out with p-type dopants.
 6. A method according to claim 1furthermore comprising, before the doping step, a step of providing afirst and a second semiconductor region.
 7. A method according to claim6, wherein the step of providing the first semiconductor regioncomprises providing a doped gate stack.
 8. A method according to claim7, wherein the step of providing a doped gate stack comprises the stepsof: growing a tunnel oxide on the semiconductor, depositing floatinggate polysilicon on the tunnel oxide, doping the floating gatepolysilicon, thus forming doped floating gate polysilicon, depositing aninterlayer dielectric on the doped floating gate polysilicon, depositingcontrol gate polysilicon on the interlayer dielectric, and doping thecontrol gate polysilicon.
 9. A method according to claim 7, furthercomprising a step of patterning the doped gate stack.
 10. A methodaccording to claim 1, wherein the oxidising step is a wet oxidationprocess.
 11. A non-volatile memory element having a memory gate stackisolated from an access gate obtained by the method of claim
 1. 12. Anon-volatile memory element according to claim 11 wherein the element isa 2-T flash EEPROM cell.